Cadence HIT-Kit v3.72 Release Notes

October 2007

 

 

 

This new HIT-Kit v3.72, qualified for Cadence IC 5.1.41 and for the technologies

  • 0.35µm H35B3 (HV CMOS, 3-metal)
  • 0.35µm H35B4 (HV CMOS, 4-metal)

contains proven features, a variety of improvements and new extensions summarized in the following overview

 

Related Design
Documents

General

  • Qualified for Solaris 7/ 8/ 9 + Red Hat Linux 7.3 + Red Hat EL 3.0
  • Layout verification tool Assura 3.1.5
  • CDL netlisting fully supported to generate Calibre netlists
  • Graphical interface for Safe-Operating-Area-Check (SOAC)
  • Full Setup and support for Cadence Multipart Paths objects
  • Improved Monte Carlo simulation models
  • Technology specific setup files for Synopsys Synthesis, VITAL, Verilog, Cadence PKS, and TLF.
  • Libraries tested and qualified for Cadence NC-Sim (NC-Verilog, NC-VHDL and VerilogXL) and ModelSim 6.3
  • Support for CDS AMS Designer + UltraSim
  • Design Rules and Process Parameter documents available on asic.austriamicrosystems.com/download
  • Synopsys, VITAL, PKS, TLF and Verilog libraries
  • First Encounter libraries available.
    •

Updates

  • Additional Devices
       NMOS20T
       NMOS20M
       NMOS20H
       NMOS20HS
       NMOSI20T
       NMOSI20M
       PMOS20T
       PMOS20M
       PMOS20M
       PMOS20HS
     
  • Additional Driver Transistors
       NMOSDI20H
       NMOSDI50H
     
  • Calibre and Assura runsets updated according to ENG-243 Rev 6.0 and ENG-292 Rev 2.0
  • Circuit Simulator models updated according to ENG-238 Rev. 5.0 and ENG-291 Rev 2.0
  • Safe Operating Area Checker updated according to ENG-238 Rev. 5.0 and ENG-291 Rev 2.0
     
  • Additional Clock-Gating Cell included in all digital Libraries
  • Library characterization up to 150 degrees
  • Fire & Ice Parasitic extraction supported
  • Enhanced Encounter Setup
     
  • All parasitic devices included in models -> no parasitic model necessary
  • Corrected errors with DC-Operating Point back annotation in Spectre
  • Disabled some false warnings from Spectre BSIM models
  • Additional element 'short' for simulation and checking of metal lines
  • Callback available, which can evaluate expressions
  • Corner Tool updated
     
  • Perimeter extraction of diodes changed - only physical junctions extracted
  • Additional Rules for checking parasitic diodes implemented
  • Changed DIODE layer in nearly all IO-Cells because of additional Design Rules
  • 'probepad' supported in Assura and Calibre
  • Guard Ring Generator enhanced

Available
Libraries

  • PRIMLIB: Includes all primitive devices (Low-Voltage and High-Voltage Devices)
     
  • CORELIB_HV Floating library Digital Standard Cells
  • IOLIB_HV_3M Floating library (3 Metal Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_HV_4M Floating library (4 Metal Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_ANA_HV_3M High Voltage library (3 Metal Analog Power Supply Pads, Analog I/O Pads for 20V and 50V)
  • IOLIB_ANA_HV_4M High Voltage library (4 Metal Analog Power Supply Pads, Analog I/O Pads for 20V and 50V)
     
  • A_CELLS C35 library (Analog Standard Cells)
  • CORELIB C35 library (Digital Standard Cells)
  • IOLIB_3M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_4M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_ANA_3M C35 library (Analog Power Supply Pads, Analog I/O Pads)
  • IOLIB_ANA_4M C35 library (Analog Power Supply Pads, Analog I/O Pads)
     
  • CORELIB_3B library (3-Bus Digital Standard Cells)
  • IOLIB_3B_3M C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_3B_4M C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_ANA_3B_3M C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
  • IOLIB_ANA_3B_4M C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
     
  • IOLIBV5_3M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
  • IOLIBV5_4M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
     
  • SFCLIB_H35xx: Standard Family Cells libraries

Trademarks

Advanced Design System, RFDE and Dynamic Link are trademarks of Agilent Technologies, Inc., Cadence, the Cadence logo and First Encounter are registered trademarks, and Encounter, Assura, Cadence NCSim, PKS and BuildGates are trademarks of Cadence Design Systems, Inc., ModelSim, Artist Link and Calibre are trademarks of Mentor Graphics Corporation, Sun and Solaris are registered trademarks of Sun Microsystems, Inc., HP-UX is a registered trademark of Hewlett-Packard Company. All other trademarks are the property of their respective owners.

 

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