HIT-Kit - Mentor based design flow
Design Flow
- Framework: IC-Studio
- Schematic Design Creation: Design Architect IC
- Register Transfer Level Creation: HDL Designer
- Behavioral Modelling: VHDL * HDL-A * Verilog * VHDL-AMS * Verilog-AMS
- Logic Synthesis & Optimization: Design Compiler [Synopsys] * RTL Compiler / PKS [Cadence]
- ATPG: Tetramax [Synopsys] * Fastscan/Flextest
- Simulation:
Behavioral: ModelSim (VHDL/Verilog) * Eldo HDL-A * NCSim [Cadence]
Digital: ModelSim (VHDL/Verilog) * NCSim [Cadence]
Analog: Eldo/Eldo RF
Mixed Signal: AdvancedMS (available in Mixed-Signal HIT-Kit only)
- Place & Route: AutoCells * First Encounter [Cadence]
- Layout: IC Station * Device Generators (available in Mixed-Signal HIT-Kit only)
- Verification: Calibre/Calibre xRC * ICverify
Trademarks: ModelSim, Calibre, ICstudio, DA-IC, IC-Station, AutoCells, ADMS, Eldo, ICnet, DMGR-IC and DVE-IC are trademarks of Mentor Graphics Corporation, First Encounter is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.