| Key Features |
- Bist Implementation for synchronous ROM instances (C35/S35).
- Bist available for all sizes of c35 ROM compiler.
- Is operating on same edge / opposite edge of ROM clock.
- Signature as PASS/FAIL criteria of Bist.
|
| Test Algorithms |
The PASS/FAIL criteria is defined in a signature. The advantage of
a signature as Bist result is, that there is no change of Bist code, if
the ROM data are changed. There is no extra effort for the BIST at a
modification of the ROM code, which typically effects only on process
mask.
|
| Gate Count |
| Gate
Count |
| Process
| all ROM sizes
|
| C35
| approx. 600 - 700 gates |
|
| Deliverables |
- Required customer specification
- ROM size configuration
- ROM data file
- BIST operating on same/opposite system clock edge
- Output formats
- Verilog netlist
- VHDL netlist
Upon the specification provided a cell based netlist of the Bist circuit
is delivered, based on austriamicrosystems' c35 digital standard
cell library (CORELIB). The netlist includes the bist circuit as
well as the wrapper to the RAM block. austriamicrosystems' c35
digital standard cell library must be available at customers site.
|
| Timing Diagram |
 The PASS/FAIL criteria
is defined in a signature, which is stored in the MISR register of
the ROM bist. This signature depends on the stored ROM data. After
testing the ROM, the content of this MISR register is issued on SIGN_out
pin. This signature must be evaluated.
|
| Description |
BIST structure generation is an additional service to the
generation of ROM instances. Data is provided on a placement of a
purchase order.
mailto:ip@austriamicrosytems.com
|
