Timing Diagram

 

metROM8kx8 - c35/s35


+------------------------------------------------------------------------------+
|                                                                              |
|                        austriamicrosystems AG                                |
|          0.35um CMOS c35/s35 - met. prog. ROM8kx8 datasheet                  |
|                        Revision NC - June 2004                               |
|                                                                              |
+------------------------------------------------------------------------------+



      ROM TERMINALS
      -------------


                              +---------------------+
                              |                     |
                   CS ------->|                     |
                        m+1   |                     |<----- VDD
              AD[12:0]---/--->| met. prog. ROM8kx8  |<----- VSS
                 NRST ------->|                     |
                              |                     |
                   EN ------->|                     |
                              |                     |
                              +---------------------+
                                        |
                                        |
                                        |
                                        v
                                      DO[7:0]





          +---------------------+------+-----------------------------------+
          | Signal name         | I/O  | FUNCTION                          |
          +---------------------+------+-----------------------------------+
          | CS                  | IN   | The rising edge on CS set         |
          |                     |      | a reading operation cycle         |
          +---------------------+------+-----------------------------------+
          | AD[12:0]            | IN   | Address bus                       |
          +---------------------+------+-----------------------------------+
          | NRST                | IN   | disable memory access at          |
          |                     |      | CS rising edge - Active at 0      |
          +---------------------+------+-----------------------------------+
          | EN                  | IN   | switches the tri-state output     |
          |                     |      | on DO - asynchronous to CS signal |
          |                     |      | EN = 1 ==> output in high         |
          |                     |      | impedance state                   |
          +---------------------+------+-----------------------------------+
          | DO[7:0]             | OUT  | Data bus                          |
          +---------------------+------+-----------------------------------+
          | VDD                 | SUP  | High  level supply voltage        |
          +---------------------+------+-----------------------------------+
          | VSS                 | SUP  | Low level supply voltage          |
          +---------------------+------+-----------------------------------+




      READ CYCLE TIMING 
      -----------------
       
 
                                        CYCLE_TIME_MIN
                   |<-------------------------------------------->|
                   |          CS_HIGH_TIME                        |
                   ||<--------------------------------->|         | 
                   ||___________________________________|         |_________
               |   /|                                    \        /          
         CS ___|__/|| AD_HOLD_TIME                        \______/         
               |  |||------------->|                      |      |
               |<-||               |                      |<---->| 
         AD_SET_UP_TIME            |                     CS_LOW_TIME
               |   |               |
            __ |___|_______________|                  ________________       
          ADi \/   |                \XXXXXXXXXXXXXXXX/                \XXXXXX
            __/\___|________________/XXXXXXXXXXXXXXXX\________________/XXXXXX
                   |
                   |
                   |  ACCESS_TIME
                   |--------------->| 
           DOi     |                |  ______________________________       
            _____/XXXXXXXXXXXXXXXXXX\/                               \_______
                 \XXXXXXXXXXXXXXXXXX/\_______________________________/      
                 | |                                                  |
                 | |                                                  |
                 |                                                    | 
            ___  |                                               _____|_____
              |\ |                                              /     |
          EN  | \|_____________________________________________/|     |
              |  |                                              |     |
              |->|                                              |---->|
               LOW_Z_TIME                                    HIGH_Z_TIME  





     NRST CYCLE
     ----------


                                         
          _________                            _________________   
                   \                        | /                 \ | 
      NRST          \ ______________________|/                   \|____________
                                            |                     |
                                            |NRST_SETUP_TIME      |
                                            |<----------|-------->| 
                                            |           |NRST_HOLD_TIME                  
                           ________________________     |  __________________
                         /                         \    | /
        CS  ____________/                           \___|/