Memory Compiler for Single Port RAM in 0.8 µm CMOS

• Memory Compiler for Single Port RAM in following CMOS Technologies:
• 0.8 µm BYx - compatible with CMOS parts of the process
• 0.8 µm CXx - compatible with 5.0V CMOS parts of CXZ
• 16,384 bit maximum memory size
• 1 .. 32 bits per word
• 32 .. 16,384 words per RAM
• one data bus or separated data buses for data input/output
• dataout with tri-state condition
• memory organisation in 1 or 2 memory banks
• several length/height ratios available (depending on total size)

• Frontend services (available via Internet)
  • CADENCE
    • cell library with symbol, functional, abstract and msps view
    • TLF 3.0 timing data file
    • black box description in ASCII format
    • Verilog model with best/typical/worst timing data

     

• Backend Services (on order)
  • CADENCE
    • cell library with additional layout view with full layout data
    • flat spice netlist for LVS purpose
  • GDSII data
    • full layout data in GDSII format
    • flat spice netlist for LVS purpose

Area [mm2]
Process	1k bit	2k bit	4k bit	8k bit	16k bit
BY_	0.60	1.04	2.02	3.40	6.32
CX_	0.46	0.77	1.46	2.42	4.49

NOTE:
The area of the memories is influenced by the word/databit configuration of the specified total size and the height/width ratio of the layout. For some configurations different height/width ratios are available.

Access Time [ns]
Process	1k bit	2k bit	4k bit	8k bit	16k bit
BY_	6.0	6.0	7.0	7.0	8.0
CX_	7.0	7.0	8.0	8.0	9.0

Timing conditions:

typical process parameters VDD = 5.0V Tj = 27°C

Access Time [ns]
Process	1k bit	2k bit	4k bit	8k bit	16k bit
BY_	10.0	10.0	11.0	12.0	13.0
CX_	16.2	17.5	18.7	18.7	21.2

Timing conditions:

typical process parameters VDD = 3.3V Tj = 27°C

In the high voltage process version CXZ the memory Blocks can be used only in the fixed low voltage part (GND = 0V, VDD < 5.0V) of the design.

The SPRAM compiler system enables automatic generation of single port RAM blocks for the configurations shown above. All representations are available for a complete design flow as symbol, simulation models, and GDSII layout data. The compiler system is not included in the HIT-Kit. Memories are provided on request.

• Timing Diagram - Rev N/C - 10/00

Registered Customers can generate their required simulation model(s) directly via Internet by clicking on the model generation link below.

• Simulation Model generation