Memory Compiler for ROM in 0.8 µm CMOS

• Memory Compiler for ROM in following CMOS Technologies:
  • 0.8 µm BYx - compatible with CMOS parts of the process
  • 0.8 µm CXx - compatible with 5.0V CMOS parts of CXZ
• diffusion programmable ROMs
• 65,376 bit maximum memory size
• 1 .. 32 bits per word
• 128 .. 4096 words per ROM
• data bus with tri-state condition
• memory organisation in 1 or 2 memory banks
• several length/height ratios available (depending on total size)

• Frontend services (available via Internet)
  • CADENCE
    • cell library with symbol, functional, abstract and msps view
    • TLF 3.0 timing data file
    • black box description in ASCII format
    • Verilog model with best/typical/worst timing data
• Backend Services (on order)
  • CADENCE
    • cell library with additional layout view with full layout data
    • flat spice netlist for LVS purpose
  • GDSII data
    • full layout data in GDSII format
    • flat spice netlist for LVS purpose

Area [mm2]
Process	1k bit	2k bit	4k bit	8k bit	16k bit	64k bit
BY_	0.23	0.27	0.33	0.46	0.81	2.58
CX_	0.18	0.20	0.24	0.33	0.54	1.59

NOTE:
The area of the memories are influenced by the word/databit configuration of the specified total size and the height/width ratio of the layout. For some configurations different height/width ratios are available.

Access Time [ns]
Process	1k bit	2k bit	4k bit	8k bit	16k bit	64k bit
BY_	6.3	6.8	7.4	8.4	10.0	25.3
CX_	6.4	7.0	8.1	9.7	12.7	19.5

Timing conditions:

typical process parameters VDD = 5.0V Tj = 27°C

Access Time [ns]
Process	1k bit	2k bit	4k bit	8k bit	16k bit	64k bit
BY_	10.7	11.4	12.3	13.9	16.5	37.1
CX_	9.3	10.2	11.4	14.0	17.8	24.3

Timing conditions:

typical process parameters VDD = 3.3V Tj = 27°C

In the high voltage process version CXZ the memory Blocks can be used only in the fixed low voltage part (GND = 0V, VDD < 5.0V) of the design.

The ROM compiler system enables automatic generation of ROM memory blocks for the configurations shown above. All representations for a complete design flow as symbol, simulation models, GDSII layout data are available. The compiler system ist not included in the HIT-Kit. Memories are provided on request.

• Timing Diagram - Rev N/C - 10/00

Registered Customers can generate their required simulation model(s) directly via Internet by clicking on the model generation link below.

• Simulation Model generation