Memory Compiler for Dual Port RAM in 0.35µm CMOS (C35)

• Memory Compiler for Dual Port RAM in 0.35µm CMOS Process (C35/S35)
• triple metal layout data of memory
• full read/write capability on each port
• 65536 bit maximum memory size
• 8 .. 32 bits per word
• 128 .. 8192 words per DPRAM
• Simulation models for 3.3V nominal supply
• 2 separated or 1 common datain/dataout buses per port
• tri-state dataout bus

• Frontend services (available via Internet)
  • CADENCE
    • cell library with symbol, functional, abstract and msps view
    • TLF 3.0 & TLF 4.3 timing data file
    • LEF file for silicon ensemble
    • SDF annotable Verilog model
  • VHDL
    • VITAL95 compliant simulation model
    • TLF timing data file for SDF generation
    • LEF file for silicon ensemble
  • SYNOPSYS
    • cell timing model (interface model)
  • MENTOR
    • Design Architect symbol
    • QSIM II simulation model & black box desription
    • black box desription
• Backend Services (on order)
  • CADENCE
    • cell library with additional layout view with reduced layout data (*)
  • gds2 data
    • reduced layout data in gds2 format (*)

  (*) reduced layout data does not contain the following layers:

  • Diffusion
  • Poly1
  • N+ Implant
  • P+ Implant
  • Contact
  The reduced layout data will be replaced with full layout data by austriamicrosystems before production.

Area [mm2]
Process	1k bit	2k bit	4k bit	8k bit	16k bit	32k bit	64k bit
C35	0.34	0.48	0.75	1.26	2.23	3.78	7.15

NOTE:
For many configurations different height/width rations are available. The aspect ratio influences area and timing data. The specified data are for the configuration, which gives the maximum density of the memory.

Access Time [ns]
Process	1k bit	2k bit	4k bit	8k bit	16k bit	32k bit	64k bit
C35	2.93	3.07	3.33	3.42	3.54	4.41	4.69

Supply Current [mA/MHz]
Process	1k bit	2k bit	4k bit	8k bit	16k bit	32k bit	64k bit
C35	0.175	0.196	0.239	0.255	0.279	0.362	0.402

Power and Timing data conditions:

typical process parameters VDD = 3.3V Tj = 27°C Cload = 1pF

The DPRAM memory compiler system enables automatic generation of dual port RAM blocks for the configurations shown above. The compiler system ist not included in a HIT-Kit shipment. Memory Simulation models are distributed via Internet (see beyond), layout data are provided on request.

All data shown in this document are related to Revision "D" of the dual port RAM compiler for 0.35um process..

• Timing Diagram - Rev A - 01/00

Registered Customers can generate their required simulation model(s) directly via Internet by clicking on the model generation link below.

• Simulation Model generation - Compiler Rev. NC