0.8痠 ECL Standard Cells (BYB, BYE)

Core Cells

**Buffers, Inverters**
Cellname	Speed	Type
EBF1H	High	ECL
EBF1M	Medium	ECL
EBF1L	Low	ECL
CBF1H	High	CML
CBF1M	Medium	CML
CBF1L	Low	CML

**Two Input AND, NAND Gates**
Cellname	Speed	Type
ELG2H	High	ECL
ELG2M	Medium	ECL
ELG2L	Low	ECL
CLG2H	High	CML
CLG2M	Medium	CML
CLG2L	Low	CML

**Three Input AND, NAND Gates**
Cellname	Speed	Type
ELG3H	High	ECL
ELG3M	Medium	ECL
ELG3L	Low	ECL
CLG3H	High	CML
CLG3M	Medium	CML
CLG3L	Low	CML

**Two Input XOR, XNOR Gates**
Cellname	Speed	Type
EEO1H	High	ECL
EEO1M	Medium	ECL
EEO1L	Low	ECL
CEO1H	High	CML
CEO1M	Medium	CML
CEO1L	Low	CML

**Logic Reference Cells**
Cellname	Speed	Type
ELOGM	Medium	ECL
CLOGM	Medium	CML

**D-Type Flip-Flop with Set**
Cellname	Speed	Type
EDF9H	High	ECL
EDF9M	Medium	ECL
EDF9L	Low	ECL
CDF9H	High	CML
CDF9M	Medium	CML
CDF9L	Low	CML

**Data Latch with Set**
Cellname	Speed	Type
EDL9H	High	ECL
EDL9M	Medium	ECL
EDL9L	Low	ECL
CDL9H	High	CML
CDL9M	Medium	CML
CDL9L	Low	CML

**2:1 Multiplexers**
Cellname	Speed	Type
EMU2H	High	ECL
EMU2M	Medium	ECL
EMU2L	Low	ECL
CMU2H	High	CML
CMU2M	Medium	CML
CMU2L	Low	CML

**Level Converter Cells**
Cellname	Speed	Type
ECC1L	Low	ECL, CML -> CMOS
ECC1S	Slow	ECL, CML -> CMOS
CEC1L	Low	CMOS -> ECL
CEC1S	Slow	CMOS -> ECL

**Bias Generators for Core Cells**
Cellname	Process
EBIAS2	BYB
EBIAS3	BYE

Periphery Cells

**100K PECL Input Cells**
Cellname	Speed	Input type
EIHD8H	High	Differential
EIHD8M	Medium	Differential
EIHS8H	High	Single-ended
EIHS8M	Medium	Single-ended

**100K PECL Reference Generator**
Cellname	Output type
EVBB	Single-ended

**100K PECL Output Cells**
Cellname	Speed	Output type
EOHD8H	High	Differential
EOHD8M	Medium	Differential
EOHS8H	High	Single-ended
EOHS8M	Medium	Single-ended

Other ECL Related Documents:

Introduction to ECL cells
Difference between ECL and CML Cells
Pseudo ECL Levels
Derating Curves
ECL Design Guidelines

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